The present invention relates to a method for automatically designing semiconductor integrated circuits, and in particular to a method for the design of large-scale integrated circuits (LSI).
Typical LSI design processing is divided into three design steps, namely the design of function, the design of logic and the design of layout. In the function design step, a functional specification is created by a hardware description language such as Verilog-HDL and VHDL or by paperwork. In the logic design step, logical data is generated from functional data describing the functional specification. The logical data is represented in the form of a netlist or in the form of a circuit diagram. In the layout design step, layout data is generated from the logical data. The layout data represents an actual mask layout. Each of these design steps has been automated with the aid of CAD tools or performed by manpower.
In the layout design of LSIs such as microcontrollers and microprocessors a design style, in which peripheral circuit blocks including floating point arithmetic units (FPUs) and user logic circuits (ULCs) are combined around a circuit block of a central processing unit (CPU) serving as a core, has been considered a practical design style. Such a ULC is a circuit block for the customization of LSI. Either custom layout design work by manpower or layout design work by automatic placement/wire routing tool is selected from the view points of, for example, required performance, cost and number of development steps for each circuit block. Custom layout design is adopted, especially for high-speed circuit blocks, to make it possible to use dedicated cells as well as to make the most of special circuit configurations, and layout editors or the like are prepared for the custom layout design. Layout design by automatic placement/wire routing tool using standard cells and gate arrays, is adopted for other circuit blocks. After all circuit blocks of the LSI are layout designed, the assembling of the circuit blocks is executed by block-to-block automatic placement/wire routing tool.
For the realization of high-efficiency LSI automated design, a technique has been proposed recently in which circuit data about individual components of each LSI which had been designed before (herein after called the predesigned LSI) are accumulated as design resources (assets) for future use. This technique is called the "resource reusing design". The circuit data is the data which includes functional data, logical data and layout data. For instance, a microcontroller LSI comprises a CPU as a core component and a plurality of peripheral components such as FPUs and ULCs. Every time a design of one microcontroller LSI is produced, circuit data about individual components of the LSI are entered into a library. Where a new LSI is a combination of preentered (already-stored) circuit components, circuit data about these preentered circuit components stored in the library are reused.
The above-described technique, however, has the problem that, even if fixed layout data about individual circuit blocks of a predesigned LSI are stored in the library for future use, these layout data are most unlikely to be used effectively when a new LSI greatly differs from the predesigned LSI in entire geometric form and in circuit block placement. In other words, there have been no means capable of utilizing results of the custom layout design produced by human designers.
If the internal module configuration and terminal placement of a core component is determined so that the core component can be connected with all peripheral components thereof, the core component then becomes redundant. One reason for the redundancy problem is that there are cases in which certain internal modules and terminals of a CPU necessary for one FPU are not needed by another FPU. In order to cope with such a situation, a method has been employed in which the internal module configuration and terminal placement of a core component is determined such that the core component can be connected with a specific group of peripheral components and circuit data about the core component is entered into the library. Therefore, even when a new LSI is a combination of preentered components, it is most likely to occur that the circuit data of the core component must be modified. If every modified circuit data is stored as a design resource, this requires a mass storage library. For this reason, conventionally, results of the modification of core component circuit data are not stored.